Until recently, efficiency increases of power conversion circuits were primarily driven by increased power density requirements. Generally, it is well known that to increase power density, incremental improvements in full-load efficiency must be made in order to ensure that the thermal performance is not adversely affected. However, today, the power supply industry is at the beginning of a major focus shift that puts efficiency improvements across the entire load range in the forefront of customers' performance requirements. This focus on efficiency has been prompted by economic reasons and environmental concerns caused by the continuous, aggressive growth of the Internet infrastructure and a relatively low energy efficiency of its power delivery system. In fact, the environmental concerns have prompted Environmental Protection Agency (EPA) to revise its Energy Star specifications for power supply efficiencies by defining the minimum efficiencies from full load down to 20% of full load. However, major computer, telecom, and network-equipment manufacturers are already demanding light-load efficiencies exceeding the latest Energy Star specifications and also are extending these requirements down to 10% and, even 5% loads.
In general, the efficiency of power conversion circuits at heavy loads is determined by conduction losses of semiconductor and magnetic components, whereas the efficiency of these power conversion circuits at light loads are primarily determined by switching losses of semiconductors, core losses of magnetics, and drive losses of semiconductor switches. Because switching and drive losses of semiconductor switches and core losses of magnetic components are almost independent of the load current, a typical efficiency curve as a function of the load current exhibits a steep decline as the load current decreases within 20-30% of the full load current. In fact, for a typical power converter, the light load efficiency, e.g., efficiency at 10%, is significantly lower than that at full load.
Generally, minimization of the conduction losses to optimize the full-load efficiency requires maximization of the silicon area and minimization of the resistance of copper conductors. Specifically, the minimization of the semiconductor conduction loss calls for the selection of MOSFETs with minimum on-resistances and rectifiers with minimum forward voltage drops, whereas the conduction loss of magnetic components such as input- and output-filter inductors, transformers, and interconnect losses, are minimized by reducing the resistance of copper conductors, i.e., by shortening the length and increasing the cross-section of wires and PCB traces. The minimization of core losses of magnetic components, switching losses of semiconductors, and drive losses is based on the selection of the optimal switching frequency and the use of low-loss magnetic materials, MOSFET switches with inherently lower switching losses, and rectifiers with a low reverse-recovery charge and/or by employing various soft-switching techniques that substantially reduce switching losses of semiconductors.
In general, established efficiency optimization techniques for power supplies are very often incapable of delivering an efficiency curve that meets customers' expectations across the entire load range. This is especially true for alternating current (AC)/direct current (DC), e.g., off-line, power supplies intended for high-power applications. In this case, it is a common practice to resort to power-supply-level power management techniques to further improve partial-load efficiencies. Generally, these power-supply-level power management techniques are based on changing an operation mode according to the load current and/or input voltage conditions. Conventional power management techniques may include variable switching frequency control, bulk-voltage reduction technique, phase-shedding technique, and “burst”-mode operation technique. While all these load-activity-based power management techniques have been implemented using analog technology, the current rapid employment of digital technology in power conversion applications has made their implementation much easier.
In off-line converters that require an active power-factor-correction (PFC) front-end, reduction of the energy-storage (bulk) voltage was extensively used to improve the efficiency over the line voltage range. This method is based on the fact that the switching losses in semiconductor components such as MOSFET switches and fast-recovery diode rectifiers are reduced if the voltage that they need to switch off is reduced. In a typical universal-line (e.g., 90-264 Vrms) AC/DC power supply with a PFC front end, the bulk voltage is set at a lower value at a low line voltage, and increased, either linearly or nonlinearly, to a higher value as the peak of the line voltage increases. The bulk capacitor value is determined such that the bulk capacitor can support the full power for a specified hold-up time (usually in the 12-ms to 20-ms range) at the minimum bulk voltage value. The range of the bulk voltage is limited by the regulation-range of the downstream DC/DC output stage.
Known technique disclosed in U.S. Pat. No. 5,349,284 positions the intermediate bulk voltage based solely on the peak of the input voltage. In other words, the intermediate bulk voltage is set greater than and proportional to the peak input voltage in order to improve the efficiency of the PFC boost stage over the universal line range (i.e., 65-265 VAC).
Known techniques disclosed in U.S. Pat. No. 5,289,361 and U.S. Pat. No. 5,406,192 position the intermediate bulk voltage based on the input voltage and the operating range of a load converter. In general, the intermediate bulk voltage is always set higher than the peak input voltage, and is adjusted either linearly or nonlinearly between two limits that are chosen based on the voltage operating range of a load converter.
Although the described techniques have led to an improvement in efficiency over a wide line voltage range, they suffer from some major drawbacks that limit their area of application. Namely, they do not take advantage of the fact that the intermediate bulk voltage can be lowered as the output power decreases, leading to a significantly reduced partial-load efficiency. Another major drawback of the known techniques is that in applications which have a hold-up time requirement, the bulk capacitor value and volume is excessively large, since it must store enough energy at the minimum intermediate bulk voltage to permit the load converters to regulate the output voltage during the hold-up time. As the line voltage increases and the intermediate bulk voltage is increased by the controller, or as the output power decreases, the bulk capacitor stores superfluous energy which is unnecessary to meet the specifications. Moreover, the volume of the bulk capacitor is determined largely by the maximum intermediate bulk voltage value.
Another major concern with the described intermediate bulk-voltage reduction and stage-shedding techniques described is the dynamic performance. Specifically, their ability to restore full-power capability without output disturbance or other performance deterioration when the load suddenly changes from light load to full load.
In this invention, implementations of power converters that offer maximized light-load efficiencies without the limitations of prior-art techniques are described.